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RM0453
38.13.10 CPU2 ROM1 CoreSight component identity register 3
(C2ROM1_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.13.11 CPU2 ROM1 register map
Table 285. CPU2 processor ROM table register map and reset values
Offset Register name
C2ROM1_
MEMTYPER
0xFCC
Reset value
C2ROM1_PIDR4
0xFD0
Reset value
0xFD4-
Reserved
0xFDC
C2ROM1_PIDR0
0xFE0
Reset value
C2ROM1_PIDR1
0xFE4
Reset value
C2ROM1_PIDR2
0xFE8
Reset value
C2ROM1_PIDR3
0xFEC
Reset value
C2ROM1_CIDR0
0xFF0
Reset value
C2ROM1_CIDR1
0xFF4
Reset value
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
r
r
Reserved.
RM0453 Rev 5
Debug support (DBG)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PREAMBLE[27:20]
r
r
r
r
F4KCOUNT
[3:0]
0
0
1
1
JEP106ID
[3:0]
1
0
0
0
REVAND[3:0] CMOD[3:0]
0
0
0
0
CLASS[3:0]
0
0
17
16
Res.
Res.
1
0
r
r
1
JEP106CON
[3:0]
0
0
0
1
0 0
PARTNUM[7:0]
0
0
0
0
0 0
PARTNUM
[11:8]
1
1
0
1
0 0
0
0
1
0
1 1
0
0
0
0
0 0
PREAMBLE[7:0]
0
0
1
1
0 1
PREAMBLE
[11:8]
0
1
0
0
0 0
1421/1450
1435
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