STMicroelectronics STM32WL5 Series Reference Manual page 104

Embedded flash memory (FLASH)
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
If a loop is present in the current buffer, no new access is performed.
CPU1 instruction cache memory (I-Cache)
To limit the CPU1 time lost due to jumps, it is possible to retain 32 lines of 4 x 64 bits
(1 Kbyte) in an instruction cache memory.This feature is enabled for the CPU1 by setting the
instruction cache enable (ICEN) bit in FLASH_ACR. Each time a miss occurs (requested
data not present in the currently used instruction line, in the prefetched instruction line or in
the instruction cache memory), the line read is copied into the instruction cache memory. If
some data contained in the instruction cache memory are requested by the CPU1, they are
provided without inserting any delay. Once all the instruction cache memory lines have been
filled, the LRU (least recently used) policy is used to determine the line to replace in the
instruction memory cache. This feature is particularly useful in case of code containing
loops.
The instruction cache memory is enabled after system reset.
CPU1 data cache memory (D-Cache)
CPU1 literal pools are fetched from the flash memory through the DCode bus during the
execution stage of the CPU1 pipeline. Each CPU1 DCode bus read access fetches 64 bits
that are saved in a current buffer. The CPU1 pipeline is consequently stalled until the
requested literal pool is provided. To limit the time lost due to literal pools, accesses through
the AHB data bus DCode have priority over accesses through the AHB instruction bus
ICode.
If some literal pools are frequently used, the CPU1 data cache memory can be enabled by
setting the data cache enable (DCEN) bit in FLASH_ACR. This feature works like the
instruction cache memory but the retained data size is limited to eight lines of 4 x 64 bits
(256 bytes).
The data cache memory is enabled after system reset.
Note: The D-Cache is active only when data is requested by the CPU1 (not by DMAs).
Data in option bytes block are not cacheable.
CPU2 cache memory (S-bus)
To limit the CPU2 time lost due to jumps, it is possible to retain four lines of 64 bits (32
bytes) in an instruction cache memory.This feature can be enabled for the CPU2 by setting
the instruction cache enable (ICEN) bit in FLASH_C2ACR. Each time a miss occurs
(requested data not present in the currently used instruction line, in the prefetched
instruction line or in the instruction cache memory), the line read is copied into the
instruction cache memory. If some data contained in the instruction cache memory are
requested by the CPU2, they are provided without inserting any delay. Once all the
instruction cache memory lines have been filled, the LRU (least recently used) policy is used
to determine the line to replace in the instruction memory cache. This feature is particularly
useful in case of code containing loops.
The instruction cache memory is enabled after system reset.
CPU2 literal pools are fetched from the flash memory through the S-bus during the
execution stage of the CPU2 pipeline. Each CPU2 S-bus read access fetches 64 bits that
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