STMicroelectronics STM32WL5 Series Reference Manual page 509

RM0453
EXTI
Acronym
o
n
14 EXTI[14]
15 EXTI[15]
16 PVD
17 RTC_ALARM
18 SSRU
TAMP,
19 RTC_STAMP,
LSE_CSS
20 RTC_WKUP
21 COMP1
22 COMP2
23 I2C1 wake-up
24 I2C2 wake-up
25 I2C3 wake-up
26 USART1
27 USART2
28 LPUART1
29 LPTIM1 wake-up
30 LPTIM2 wake-up
31 LPTIM3 wake-up
32 Reserved
33 Reserved
34 PVM[3]
35 Reserved
36 IPCC CPU1
37 IPCC CPU2
38 HSEM interrupt 0
39 HSEM interrupt 1
40 C2SEV
41 C1SEV
42 Flash
HSE32 CSS
43
interrupt
44 Radio IRQs
Table 93. Wake-up interrupts (continued)
Description
EXTI line 14 from SYSCFG
EXTI line 15 from SYSCFG
PVD line
RTC alarms A and B interrupt
RTC SSR underflow interrupt
TAMP tamper interrupt
RTC timestamp interrupt
RCC LSECSS interrupt
RTC wake-up interrupt
COMP1 line
COMP2 line
I2C1 wake-up
I2C2 wake-up
I2C3 wake-up
USART1 wake-up
USART2 wake-up
LPUART1 wake-up
LPtimer 1 wake-up
LPtimer 2 wake-up
LPtimer 3 wake-up
-
-
PVM[3] line
-
IPCC CPU1 RX occupied and TX free
interrupts
IPCC CPU2 RX occupied and TX free
interrupts
Semaphore interrupt 0 with CPU1
Semaphore interrupt 1 with CPU2
CPU2 SEV line
CPU1 SEV line
Flash ECC and global interrupts
RCC HSE32 CSS interrupt
Radio IRQs interrupts
RM0453 Rev 5
Extended interrupts and event controller (EXTI)
EXTI type
Configurable
Configurable
Configurable
Direct
Direct
Direct
Direct
Configurable
Configurable
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Configurable
Direct
Direct
Direct
Direct
Direct
Configurable
Configurable
Direct
Direct
Direct
Event Wake-up
Yes CPU1 and CPU2
Yes CPU1 and CPU2
No CPU1 and CPU2
Yes CPU1 and CPU2
Yes CPU1 and CPU2
Yes CPU1 and CPU2
Yes CPU1 and CPU2
Yes CPU1 and CPU2
Yes CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No -
No -
No CPU1 and CPU2
No -
(1)
No CPU1
(2)
No CPU2
(1)
No CPU1
(2)
No CPU2
(3)
Yes CPU1
(4)
Yes CPU2
No CPU1 and CPU2
No CPU1 and CPU2
No CPU1 and CPU2
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