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Debug support (DBG)
38.14.12 BPU CoreSight component identity register 3 (BPU_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.14.13 CPU2 BPU register map
Offset Register name
BPU_CTRLR
0x000
Reset value
BPU_REMAPR
0x004
Reset value
BPU_COMP0-7R
0x008 to
0x024
Reset value
0x02C-
Reserved
0xFCC
BPU_PIDR4
0xFD0
Reset value
0xFD4-
Reserved
0xFDC
BPU_PIDR0
0xFE0
Reset value
BPU_PIDR1
0xFE4
Reset value
1434/1450
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
Table 287. CPU2 BPU register map and reset values
0
0
0
0
0
0
0
0
0
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
r
r
0
COMP[26:0]
0
0
0
0
0
0
0
0
0
Reserved.
Reserved.
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PREAMBLE[27:20]
r
r
r
r
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
F4KCOUNT
[3:0]
0
0
0
0
JEP106ID
[3:0]
1
0
RM0453
17
16
Res.
Res.
1
0
r
r
0
0
0 0
0
0
0
0
0
JEP106CON
[3:0]
0
0
0
1
0 0
PARTNUM[7:0]
0
0
1
1
0 0
PARTNUM
[11:8]
1
1
0
0
0 0
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