STMicroelectronics STM32WL5 Series Reference Manual page 519

RM0453
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 FT45: falling trigger event configuration bit of configurable event input 45
Note: The configurable event inputs are edge triggered. No glitch must be generated on
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 FT41: falling trigger event configuration bit of configurable event input 41
Bit 8 FT40: falling trigger event configuration bit of configurable event input 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 FT34: falling trigger event configuration bit of configurable event input 34
Bits 1:0 Reserved, must be kept at reset value.
16.6.7 EXTI software interrupt event register (EXTI_SWIER2)
Address offset: 0x028
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. SWI45 Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 SWI45: software interrupt on event 45
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 SWI41: software interrupt on event 41
Bit 8 SWI40: software interrupt on event 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 SWI34: software interrupt on event 34
Bits 1:0 Reserved, must be kept at reset value.
0: Falling trigger disabled (for event and interrupt) for input line
1: Falling trigger enabled (for event and interrupt) for input line
these inputs. If a falling edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. SWI41
rw
A software interrupt is generated independently from the setting in EXTI_RTSR and
EXTI_FTSR. This bit always returns 0 when read.
0: Writing 0 has no effect.
1: Writing 1 to this bit triggers an event on line 45.
This bit is automatically cleared by hardware.
Extended interrupts and event controller (EXTI)
24 23 22
Res. Res. Res.
8 7 6
SWI40 Res. Res.
rw
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. SWI34
rw
17 16
Res. Res.
1 0
Res. Res.
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