STMicroelectronics STM32WL5 Series Reference Manual page 884

General-purpose timer (TIM2)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 CNT[31:0]: counter value
26.4.13 TIM2 counter [alternate] (TIM2_CNT)
Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in
TIMx_CR1 register:
•
Previous section is for UIFREMAP = 0
• This section is for UIFREMAP = 1
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
UIFCPY
rw rw rw
15 14 13
rw rw rw
Bit 31 UIFCPY: UIF Copy
Bits 30:0 CNT[30:0]: counter value
26.4.14 TIM2 prescaler (TIM2_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
884/1450
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
This bit is a read-only copy of the UIF bit of the TIMx_ISR register
12 11 10 9
rw rw rw rw
The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
24 23 22
CNT[31:16]
rw rw rw
8 7 6
CNT[15:0]
rw rw rw
24 23 22
CNT[30:16]
rw rw rw
8 7 6
CNT[15:0]
rw rw rw
8 7 6
PSC[15:0]
rw rw rw
CK_PSC
RM0453 Rev 5
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
5 4 3 2
rw rw rw rw
/ (PSC[15:0] + 1).
RM0453
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
1 0
rw rw