STMicroelectronics STM32WL5 Series Reference Manual page 11

RM0453
7.2.21
7.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
7.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
7.4.13
7.4.14
7.4.15
7.4.16
7.4.17
7.4.18
7.4.19
7.4.20
7.4.21
7.4.22
7.4.23
7.4.24
7.4.25
7.4.26
7.4.27
7.4.28
Peripheral clocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
RCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 307
RCC internal clock sources calibration register (RCC_ICSCR) . . . . . . 310
RCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 311
RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 314
RCC clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . 317
RCC clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . 318
RCC clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . 319
RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 321
RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 321
RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 322
RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . 323
RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . 324
RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 325
RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . . . . . . . 326
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 327
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 328
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 329
RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . 330
RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . 331
RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 332
RCC APB3 peripheral clock enable register (RCC_APB3ENR) . . . . . 333
RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
RCC AHB2 peripheral clock enable in Sleep mode register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
RCC AHB3 peripheral clock enable in Sleep and Stop mode register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
RM0453 Rev 5
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