STMicroelectronics STM32WL5 Series Reference Manual page 349

RM0453
7.4.32 RCC extended clock recovery register (RCC_EXTCFGR)
Address offset: 0x108
Reset value: 0x0003 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 C2HPREF: HCLK2 prescaler flag (CPU2)
Bit 16 SHDHPREF: HCLK3 shared prescaler flag (AHB3, flash, SRAM1, and SRAM2)
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
This bit is set and cleared by hardware to acknowledge HCLK2 prescaler programming. It is
reset when a new prescaler value is programmed in C2HPRE[3:0]. This bit is set when the
programmed value is actually applied.
0: HCLK2 prescaler value not yet applied
1: HCLK2 prescaler value applied
This bit is set and cleared by hardware to acknowledge the shared HCLK3 prescaler
programming. It is reset when a new prescaler value is programmed in SHDHPRE[3:0]. This
bit is set when the programmed value is actually applied.
0: HCLK3 prescaler value not yet applied
1: HCLK3 prescaler value applied
24 23 22
Res. Res. Res.
8 7 6
Res. C2HPRE[3:0]
rw rw
RM0453 Rev 5
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SHDHPRE[3:0]
rw rw rw rw
17 16
C2 SHD
HPREF HPREF
r r
1 0
rw rw
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