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Debug support (DBG)
38.10.13 ITM CoreSight component identity register 3 (ITM_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.10.14 CPU1 ITM register map
Offset Register name
ITM_STIM0-31R
0x000 to
0x07C
Reset value
ITM_TER
0x080
Reset value
0x084 to
Reserved
0xDCC
ITM_TPR
0xE00
Reset value
0xE04 to
Reserved
0xE4C
ITM_TCR
0xE80
Reset value
0xE84 to
Reserved
0xFCC
ITM_PIDR4
0xFD0
Reset value
0xFD4 to
Reserved
0xFDC
ITM_PIDR0
0xFE0
Reset value
ITM_PIDR1
0xFE4
Reset value
1394/1450
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
Table 280. CPU1 ITM register map and reset values
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
r
r
STIMULUS[31:0]
x
x
x
x
x
x
x
x
x
STIMENA[31:0]
0
0
0
0
0
0
0
0
0
Reserved.
PRIVMASK[31:0]
0
0
0
0
0
0
0
0
0
Reserved.
TRACEBUSID[6:0]
0
0
0
0
0
0
0
Reserved.
Reserved.
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PREAMBLE[27:20]
r
r
r
r
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F4KCOUNT
[3:0]
0
0
0
0
JEP106ID
[3:0]
1
0
RM0453
17
16
Res.
Res.
1
0
r
r
x
x
x
x
x
x
0
0
0
0
0 0
0
0
0
0
0 0
0
0
0
0 0
JEP106CON
[3:0]
0
0
0
1
0 0
PARTNUM[7:0]
0
0
0
0
0 1
PARTNUM
[11:8]
1
1
0
0
0 0
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