STMicroelectronics STM32WL5 Series Reference Manual page 643

RM0453
Bit 31 CONFIGLOCK: RNG Config lock
Bit 30 CONDRST: Conditioning soft reset
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:20 RNG_CONFIG1[5:0]: RNG configuration 1
Bits 19:16 CLKDIV[3:0]: Clock divider factor
Bits 15:13 RNG_CONFIG2[2:0]: RNG configuration 2
Bit 12 NISTC: NIST custom
Bits 11:8 RNG_CONFIG3[3:0]: RNG configuration 3
Bit 7 Reserved, must be kept at reset value.
Bit 6 Reserved, must be kept at reset value.
0: Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are allowed.
1: Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next
RNG reset.
This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset.
Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new
RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_HTCR are
not changed by CONDRST.
This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other
words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be
written.
When CONDRST is set to 0 by the software, its value goes to 0 when the reset process is
done. It takes about 2 AHB clock cycles + 2 RNG clock cycles.
Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended
value documented in Section 22.6: RNG entropy source
Writing any bit of RNG_CONFIG1 is taken into account only if the CONDRST bit is set to 1 in
the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if
CONFIGLOCK = 1.
This value used to configure an internal programmable divider (from 1 to 16) acting on the
incoming RNG clock. These bits can be written only when the core is disabled (RNGEN = 0).
0x0: internal RNG clock after divider is similar to incoming RNG clock.
0x1: two RNG clock cycles per internal RNG clock.
2
0x2: 2 (= 4) RNG clock cycles per internal RNG clock.
...
15
0xF: 2 RNG clock cycles per internal clock (for example. an incoming 48 MHz RNG clock
becomes a 1.5 kHz internal RNG clock)
Writing these bits is taken into account only if the CONDRST bit is set to 1 in the same
access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1.
Reserved to the RNG configuration (bitfield 2). Refer to the RNG_CONFIG1 bitfield for
details.
0: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output
two conditioning loops are performed and 256 bits of noise source are used.
1: Custom values for NIST compliant RNG. See
validation for proposed configuration.
Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access,
while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1.
Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details.
If the NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by
RNG.
True random number generator (RNG)
Section 22.6: RNG entropy source
RM0453 Rev 5
validation.
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