Table 67. Ipcc Interface Signals; Figure 36. Ipcc Block Diagram - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
The channel operation mode must be known to both processors. A common parameter can
be used to indicate the channel transfer mode and must also be located in a known common
area. This parameter is not available from the IPCC.
9.3.1 IPCC block diagram
The IPCC (see
•
Status block, containing the channel status
•
IPCC interface block, providing AHB access to the channel status registers
•
Interrupt interface block, providing control for the interrupts
AHB slave
AHB slave
ipcc_tx_free_int1
ipcc_rx_occupied_int1
ipcc_tx_free_int2
ipcc_rx_occupied_int2
9.3.2 IPCC Simplex channel mode
In Simplex channel mode, a dedicated memory location (used to transfer data in a single
direction) is assigned to the communication data. The associated channel N control bits
(see Table
Figure 36) consists of the following subblocks:

Figure 36. IPCC block diagram

IPCC STATUS
STATUS
Channel 1
STATUS
Channel N
IPCC
INTERFACE
STATUS
Channel 1
STATUS
Channel N

Table 67. IPCC interface signals

Signal
Name
68) are used to manage the transfer from the sending to the receiving processor.
Inter-processor communication controller (IPCC)
IPCC
INTERRUPT
GENERATION
1TO2
1TO2
Interrupt
generation
2TO1
2TO1
Type
I/O AHB register access bus
O TX free interrupt to processor 1
O RX occupied interrupt to processor 1
O TX free interrupt to processor 2
O RX occupied interrupt to processor 2
RM0453 Rev 5
ipcc_tx_free_int0
ipcc_rx_occupied_int0
ipcc_tx_free_int1
ipcc_rx_occupied_int1
MS42429V1
Description
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