Figure 135. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded); Figure 136. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded) - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Figure 135. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
Timerclock = CK_CNT
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Figure 136. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload shadow
Write a new value in TIMx_ARR
CK_PSC
CEN
31
Counter register
Counter overflow
FF
Write a new value in TIMx_ARR
CK_PSC
CEN
F0
(UIF)
F5
register
register
preloaded)
32 33 34 35 36
preloaded)
F1 F2 F3 F4 F5
F5
RM0453 Rev 5
Advanced-control timer (TIM1)
00
01 02 03 04 05
36
00 01 02 03 04 05 06 07
36
36
06
07
MS31082V3
MS31083V2
729/1450
821