Figure 384. Block Diagram Of Debug Support Infrastructure - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
38.2 DBG use cases
The trace and debug system is designed to support a variety of typical use cases:
•
Low-cost trace
Limited trace capability is available over the single-wire debug output. This supports
code instrumentation using printf, tracing of data and address watchpoints, interrupt
detection and program counter sampling. Single-wire trace can be maintained even
when one or both processors are switched off or clock-stopped.
• Breakpoint debugging of each core independently
Both processor cores can be simultaneously and independently debugged using
equipment connected to the JTAG/SWD debug port. This enables, among others,
breakpoint and watchpoint setting, code stepping and memory access.
•
Synchronous debugging of both cores
When one core stops due to a breakpoint or a debugger stop command, the other core
can be stopped as well. Similarly, the cores can be restarted at the same time. This
allows the user to debug loosely coupled applications, which require the processors to
remain synchronized.
• Tracing code execution via the trace port
Trace information from the CPU1 (Cortex-M4) is combined into a single trace stream
and sent to a trace port analyzer in real time. An ID embedded in the trace allows the
analyzer to identify the source of each information packet.
38.3 DBG functional description
38.3.1 DBG block diagram

Figure 384. Block diagram of debug support infrastructure

JTAG/Serial-wire port
JTMS/SWDIO
JTDI
JTDO
JTCK/SWCLK
nJTRST
(1) Arm CoreSight components
Debug access
port (DAP)
SWJ-DP
(1)
CPU1
Cortex-M4
(1)
AHB-AP
AHB
ROM1
(1)
table
BPU
RM0453 Rev 5
(1) (1)
DWT FPB ITM
AHB
ROM
Core
table
PPB
(1)
CTI
Cross trigger matrix (CTM)
(1)
CTI
ROM2
Core
(1)
table
CPU2
(1) (1)
DWT
Cortex-M0+
Debug support (DBG)
Trace port
(1)
(1)
TPIU
TRACESWO
(1)
DBG_MCU
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