Figure 151. Control Circuit In Normal Mode, Internal Clock Divided By 1 - STMicroelectronics STM32WL5 Series Reference Manual

Advanced-control timer (TIM1)
25.3.5 Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin
•
External clock mode2: external trigger input ETR
•
Encoder mode
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 151
without prescaler.

Figure 151. Control circuit in normal mode, internal clock divided by 1

Counter initialization (internal)
Counter clock = CK_CNT = CK_PSC
Counter register
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
740/1450
shows the behavior of the control circuit and the upcounter in normal mode,
Internal clock
CEN=CNT_EN
UG
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RM0453 Rev 5
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RM0453
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MSv31085V3