STMicroelectronics STM32WL5 Series Reference Manual page 115

RM0453
5. Set the options start bit OPTSTRT in FLASH_CR.
6. Wait for the BSY bit to be cleared.
Note: Any modification of the value of one option is automatically performed by erasing user
option bytes pages first, and then programming all the option bytes with the values
contained in the flash option registers.
Warning:
Secure user options
When the system is secure (ESE = 1), the secure option bytes flash in FLASH_C2ACR and
FLASH_SRRVR can only be written by the secure CPU2.
Option byte loading
After the BSY bit is cleared, all new options are updated into the flash memory but not
applied to the system. A read from the option registers still returns the last loaded option
byte values. The new options have effect on the system only after they are loaded.
Option bytes loading is performed in the following two cases:
•
when OBL_LAUNCH bit is set in FLASH_CR
• after a power reset (BOR reset or exit from Standby/Shutdown modes)
Option byte loader performs a read of the options block and stores the data into internal
option registers. These internal registers configure the system and can be read by software.
Setting OBL_LAUNCH generates a reset so the option byte loading is performed under
system reset.
Each option bit has also its complement in the same double-word. During option loading, a
verification of the option bit and its complement allows the correct loading to be checked.
During option byte loading, the options are read by double-word. ECC on option words is
not taken into account during OBL but only during direct software read of option area.
If the word and its complement are matching, the option word/byte is copied into the option
register.
If the comparison between the word and its complement fails, a status bit OPTVERR is set.
Mismatch values are forced into the option registers as follows:
•
For USR OPT option, the value of mismatch is all options at '1', except for BOR_LEV
that is "000" (lowest threshold).
•
For WRP option, the value of mismatch is the default value "No protection".
•
For RDP option, the value of mismatch is the default value "Level 1".
•
For PCROP, the value of mismatch is "all memory protected".
•
For CxBOOT_LOCK option, the value of mismatch is "CPU1 boot lock disabled",
"CPU2 boot lock disabled".
On RDP regression from level 1 to level 0, starting the option
programming by the OPTSTRT bit causes the flash memory,
SRAM1 and SRAM2 to be erased. All device software in all
memories is erased. A subsequent OBL_LAUNCH must be
started by an external tool or a POR must be performed to
restart the device and reload the options.
RM0453 Rev 5
Embedded flash memory (FLASH)
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