STMicroelectronics STM32WL5 Series Reference Manual page 398

Inter-processor communication controller (IPCC)
Bits 5:0 CHnF: Processor 2 transmit to processor 1 receive channel n status flag before masking (n = 6
to 1)
1: Channel occupied, data can be read by the receiving processor 1.
Generates a channel RX occupied interrupt to processor 1, when unmasked.
0: Channel free, data can be written by the sending processor 2.
Generates a channel TX free interrupt to processor 2, when unmasked.
398/1450 RM0453 Rev 5
RM0453