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Embedded flash memory (FLASH)
Bit 8 PRFTEN: CPU1 prefetch enable
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LATENCY[2:0]: Latency
4.10.2
FLASH access control register 2 (FLASH_ACR2)
Address offset: 0x004
Reset value: 0x0000 0000 (Default)
Default reset when HDPAD = 0, 0x0000 0004 when HDPAD = 1
This register provides write access security and privilege. It can only be written by the
secure privileged CPU2. A write access from the unprivileged CPU2 or a CPU1 is ignored.
A non-secure or unprivileged write access generates an illegal access event. On any read
access, the register value is returned.
There are no read restrictions.
Note:
When the system is non-secure (ESE = 0), this register cannot be written.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
130/1450
0: CPU1 prefetch disabled
1: CPU1 prefetch enabled
These bits represent the ratio of the flash HCLK clock period to the flash memory access
time.
000: Zero wait state
001: One wait state
010: Two wait states
Others: reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
RM0453
17
16
Res.
Res.
1
0
rw
rw
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