STMicroelectronics STM32WL5 Series Reference Manual page 75

RM0453
Table 4. Memory map and peripheral register boundary addresses (continued)
Bus Boundary address
0x4000 B400 - 0x4000 FFFF
0x4000 B000 - 0x4000 B3FF
0x4000 9C00 - 0x4000 AFFF
0x4000 9800 - 0x4000 9BFF
0x4000 9400 - 0x4000 97FF
0x4000 8400 - 0x4000 93FF
0x4000 8000 - 0x4000 83FF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 6000 - 0x4000 73FF
0x4000 5C00 - 0x4000 5FFF
APB1
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4800 - 0x4000 53FF
0x4000 4400 - 0x4000 47FF
0x4000 3C00 - 0x4000 43FF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 0400 - 0x4000 27FF
0x4000 0000 - 0x4000 03FF
- 0x2220 0000 - 0x3FFF FFFF
0x2210 0000 - 0x221F FFFF
AHB3
0x2200 0000 - 0x220F FFFF
- 0x2001 0000 - 0x21FF FFFF
0x2000 8000 - 0x2000 FFFF
AHB3
0x2000 0000 - 0x2000 7FFF
- 0x1FFF 8080 - 0x1FFF FFFF
Size
Peripheral
(bytes)
- Reserved
1 K TAMP
- Reserved
1 K LPTIM3
1 K LPTIM2
- Reserved
1 K LPUART1
1 K LPTIM1
- Reserved
1K DAC
- Reserved
1 K I2C3
1 K I2C2
1 K I2C1
- Reserved
1 K USART2
- Reserved
1 K SPI2S2
- Reserved
1 K IWDG
1 K WWDG
1 K RTC
- Reserved
1 K TIM2
- Reserved
SRAM2 bit
1024 K banding (CPU1
only)
SRAM1 bit
1024 K
banding (CPU1
only)
- Reserved
32 K SRAM2
32 K SRAM1
- Reserved
RM0453 Rev 5
Peripheral register map
-
Section 33.6.11: TAMP register map
-
Section 28.7.13: LPTIM register map
Section 28.7.13: LPTIM register map
-
Section 36.7.13: LPUART register map
Section 28.7.13: LPTIM register map
-
Section 19.7.13: DAC register map
-
Section 34.7.12: I2C register map
Section 34.7.12: I2C register map
Section 34.7.12: I2C register map
-
Section 35.8.15: USART register map
-
Section 37.9.10: SPI/I2S register map
-
Section 30.4.6: IWDG register map
Section 31.5.4: WWDG register map
Section 32.6.23: RTC register map
-
Section 26.4.25: TIMx register map
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