STMicroelectronics STM32WL5 Series Reference Manual page 109

RM0453
Note: When the flash memory interface received a good sequence (a double-word),
programming is automatically launched and the BSY bit is set. The internal oscillator
HSI16 (16 MHz) is enabled automatically when the PG bit is set, and disabled
automatically when the PG bit is cleared, except if the HSI16 is previously enabled
with HSION in the RCC_CR register.
If the user needs to program only one word, double-word must be completed with the
erase value 0xFFFF FFFF to launch automatically the programming.
ECC is calculated from the double-word to program.
For correct operation, the firmware must guarantee that the flash page access
protection is not changed during the programming sequence. This is between the first
and second word write.
6. Wait until BSY is cleared in FLASH_SR or FLASH_C2SR.
7. Check that EOP is set in FLASH_SR or FLASH_C2SR (meaning the programming
operation succeeded), and clear it by software.
8. Clear PG in FLASH_SR or FLASH_C2SR if there no more programming request.
Fast programming
This mode allows a row to be programmed, 32 double-words (256 bytes), and the page
programming time to be reduced by eliminating the need for verifying the flash memory
locations before they are programmed and to avoid rising and falling time of high voltage for
each double-word. During fast programming, the flash clock frequency (HCLK3) must be at
least 8 MHz.
Fast row programming must be performed by executing firmware from SRAM and disabling
interrupts when not relocating the CPU interrupt vector table. A read access form the CPU
requesting row programming causes a bus error. A read from any other source (such as the
other CPU or DMA) is stalled until the row programming is finished (standard double-word
programming does not cause a bus error to the requesting CPU but stalls any read until
standard programming is finished).
Only the main memory can be programmed in Fast programming mode.
The flash main memory programming sequence in Fast programming mode is described
below:
1. Perform a mass erase. If not, PGSERR is set.
2. Check that no flash main memory operation is ongoing by checking BSY bit
FLASH_SR or FLASH_C2SR.
3. Check that flash memory program and erase operation is allowed by checking PESD in
FLASH_SR or FLASH_C2SR (these checks are recommended even if status may
change due to flash operation requests by the other CPU, to limit the risk of receiving a
bus error when starting programming).
4. Check and clear all error programming flag due to a previous programming.
5. Set FSTPG in FLASH_CR or FLASH_C2CR.
6. Write the 32 double-words to program a row (256 bytes).
7. Wait until BSY is cleared in FLASH_SR or FLASH_C2SR.
8. Check that the EOP flag is set in FLASH_SR or FLASH_C2SR (meaning the
programming operation succeeded), and clear it by software.
9. Clear FSTPG in FLASH_SR or FLASH_C2SR if there are no more programming
requests.
RM0453 Rev 5
Embedded flash memory (FLASH)
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