STMicroelectronics STM32WL5 Series Reference Manual page 472

Direct memory access controller (DMA)
Bit 18 SSEC: Security of the DMA transfer from the source
This bit can only be accessed - read, set or cleared - by a secure software. It must be a
privileged software if the channel is in privileged mode.
This bit is cleared by hardware when the securely written data bit 17 is cleared (on a secure
reconfiguration of the channel as non -secure).
A non-secure read to this secure configuration bit returns 0.
A non-secure write of 1 to this secure configuration bit has no impact on the register setting
and an illegal access pulse is asserted.
Source (peripheral or memory) of the DMA transfer is defined by the direction DIR
configuration bit.
0: Non-secure DMA transfer from the source
1: Secure DMA transfer from the source
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 17 SECM: Secure mode
This bit can only be set or cleared by a secure software.
0: Non-secure channel
1: Secure channel
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory-to-memory mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
Bits 13:12 PL[1:0]: Priority level
00: Low
01: Medium
10: High
11: Very high
Note: This bitfield is set and cleared by software (privileged/secure software if the channel is in
472/1450
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
RM0453 Rev 5
RM0453