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RM0453
38.9.11
FPB CoreSight component identity register 2 (FPB_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
38.9.12
FPB CoreSight component identity register 3 (FPB_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.9.13
CPU1 FPB register map
Offset Register name
FPB_CTRLR
0x000
Reset value
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
Table 279. CPU1 FPB register map and reset values
RM0453 Rev 5
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
r
r
r
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
r
r
r
0
Debug support (DBG)
20
19
18
Res.
Res.
Res.
4
3
2
PREAMBLE[19:12]
r
r
r
20
19
18
Res.
Res.
Res.
4
3
2
PREAMBLE[27:20]
r
r
r
0
0
0
0
1
0
0
1
1
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
0
0 0
1385/1450
1435
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