Figure 149. External Trigger Input Block - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
25.3.4 External trigger input
The timer features an external trigger input ETR. It can be used as:
•
external clock (external clock mode 2, see
•
trigger for the slave mode (see
•
PWM reset input for cycle-by-cycle current regulation (see
Figure 149
ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed
by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield.
ETR input
The ETR input comes from multiple sources: input pins (default configuration), comparator
outputs and analog watchdogs. The selection is done with the ETRSEL[3:0] and the
TIM1_OR1[1:0] bitfields.
ETR inputs from
AF controller
ADC_AWD1
ADC_AWD2
ADC_AWD3
below describes the ETR input conditioning. The input polarity is defined with the

Figure 149. External trigger input block

ETR
0
Divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR TIMx_SMCR
Figure 150. TIM1 ETR input circuitry
TIM1_OR1[1:0]
NC
RM0453 Rev 5
Section 25.3.5)
Section 25.3.26)
ETRP
Filter
downcounter
f
DTS
ETF[3:0]
TIMx_SMCR
TIM1_AF1[17:14]
ETR legacy mode
COMP1
COMP2
NC
NC
NC
NC
NC
Advanced-control timer (TIM1)
Section 25.3.7)
To the Output mode controller
To the CK_PSC circuitry
To the Slave mode controller
ETR input
MS34403V2
MSv47460V2
739/1450
821