STMicroelectronics STM32WL5 Series Reference Manual page 518

Extended interrupts and event controller (EXTI)
16.6.5 EXTI rising trigger selection register (EXTI_RTSR2)
Address offset: 0x020
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. RT45 Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 RT45: rising trigger event configuration bit of configurable event input 45
Note: The configurable event inputs are edge triggered. No glitch must be generated on
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 RT41: rising trigger event configuration bit of configurable event input 41
Bit 8 RT40: rising trigger event configuration bit of configurable event input 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 RT34: rising trigger event configuration bit of configurable event input 34
Bits 1:0 Reserved, must be kept at reset value.
16.6.6 EXTI falling trigger selection register (EXTI_FTSR2)
Address offset: 0x024
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. FT45 Res.
rw
518/1450
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. RT41
rw
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line
these inputs. If a rising edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. FT41
rw
24 23 22
Res. Res. Res.
8 7 6
RT40 Res. Res.
rw
24 23 22
Res. Res. Res.
8 7 6
FT40 Res. Res.
rw
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. RT34
rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. FT34
rw
RM0453
17 16
Res. Res.
1 0
Res. Res.
17 16
Res. Res.
1 0
Res. Res.