Table 282. Dbgmcu Register Map And Reset Values - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
38.12.8 DBGMCU CPU2 APB2 peripheral freeze register
(DBGMCU_C2APB2FZR)
Address offset: 0x048
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 stop in CPU2 debug
0: Normal operation. TIM17 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM17 is frozen while CPU2 is in debug mode.
Bit 17 DBG_TIM16_STOP: TIM16 stop in CPU2 debug
0: Normal operation. TIM16 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM16 is frozen while CPU2 is in debug mode.
Bits 16:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 stop in CPU2 debug
0: Normal operation. TIM1 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM1 is frozen while CPU2 is in debug mode.
Bits 10:0 Reserved, must be kept at reset value.
38.12.9 DBGMCU register map
Offset Register name
DBGMCU_
IDCODER
0x000
Reset value
DBGMCU_CR
0x004
Reset value
0x008-
Reserved
0x038
28 27 26 25
Res. Res. Res.
12 11 10 9
DBG_
TIM1 Res. Res.
_STOP
rw

Table 282. DBGMCU register map and reset values

REV_ID[15:0]
x x x x x x x x
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
x x x x x x x x
Reserved.
RM0453 Rev 5
Debug support (DBG)
21 20 19 18
DBG_
Res. Res. Res. TIM17
_STOP
rw
5 4 3 2
Res. Res. Res. Res.
DEV_ID[11:0]
0 1 0 0 1 0
17 16
DBG_
TIM16 Res.
_STOP
rw
1 0
Res. Res.
0 1 0 1 1 1
0 0 0
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