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RM0453
11.2.2
SYSCFG configuration register 1 (SYSCFG_CFGR1)
Address offset: 0x004
Reset value: 0x7C00 0001
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 I2C3_FMP: I2C3 Fast-mode Plus driving capability activation
Bit 21 I2C2_FMP: I2C2 Fast-mode Plus driving capability activation
Bit 20 I2C1_FMP: I2C1 Fast-mode Plus driving capability activation
Bit 19 I2C_PB9_FMP: Fast-mode Plus (Fm+) driving capability activation on PB9
Bit 18 I2C_PB8_FMP: Fast-mode Plus (Fm+) driving capability activation on PB8
Bit 17 I2C_PB7_FMP: Fast-mode Plus (Fm+) driving capability activation on PB7
Bit 16 I2C_PB6_FMP: Fast-mode Plus (Fm+) driving capability activation on PB6
Bits 15:9 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.
This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.
This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.
This bit enables the Fm+ driving mode for PB9.
0: PB9 pin operates in standard mode.
1: Fm+ mode enabled on PB9 pin, and the speed control is bypassed.
This bit enables the Fm+ driving mode for PB8.
0: PB8 pin operates in standard mode.
1: Fm+ mode enabled on PB8 pin, and the speed control is bypassed.
This bit enables the Fm+ driving mode for PB7.
0: PB7 pin operates in standard mode.
1: Fm+ mode enabled on PB7 pin, and the speed control is bypassed.
This bit enables the Fm+ driving mode for PB6.
0: PB6 pin operates in standard mode.
1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.
System configuration controller (SYSCFG)
24
23
22
Res.
Res.
rw
8
7
6
Res.
Res.
rw
RM0453 Rev 5
21
20
19
18
rw
rw
rw
rw
5
4
3
2
Res.
Res.
Res.
Res.
17
16
rw
rw
1
0
Res.
Res.
433/1450
445
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