Table 143. Internal Input/Output Signals; Figure 127. Pka Block Diagram - STMicroelectronics STM32WL5 Series Reference Manual

Public key accelerator (PKA)
pka_hclk
24.3.2 PKA internal signals
Table 143
bonding pads.
Signal name
pka_hclk
24.3.3 PKA reset and clocks
PKA is clocked on the AHB bus clock. The RAM receives this clock directly, the core is
clocked at half the frequency.
When the PKA peripheral reset signal is released PKA RAM is cleared automatically, taking
894 clock cycles. During this time the setting of EN bit in PKA_CR is ignored.
24.3.4 PKA public key acceleration
Overview
Public key accelerator (PKA) is used to accelerate Rivest, Shamir and Adleman (RSA),
Diffie-Hellman (DH) as well as ECC over prime field operations. Supported operand sizes is
up to 3136 bits for RSA and DH, and up to 640 bits for ECC.
The PKA supports all non-singular elliptic curves defined over prime fields, that can be
described with a short Weierstrass equation y
found in
Note: Binary curves, Edwards curves and Curve25519 are not supported by the PKA.
A memory of 3576 bytes (894 words of 32 bits) called PKA RAM is used for providing initial
data to the PKA, and for holding the results after computation is completed. Access is done
though the PKA AHB interface.
696/1450

Figure 127. PKA block diagram

AHB
interface
IRQ
pka_it
interface
lists internal signals available at the IP level, not necessarily available on product

Table 143. Internal input/output signals

Signal type
Digital input
pka_it Digital output
Section 24.5.1: Supported elliptic
Banked registers (main)
PKA_CR
control
PKA_SR
status
PKA_CLRFR
clear
Control
PKA core
logic
AHB bus clock
Public key accelerator IP global interrupt request
2 3
= x + ax + b (mod p). More information is
curves.
RM0453 Rev 5
PKA32
894x32-bit
PKA RAM
32-bit
Description
RM0453
MS45419V1