STMicroelectronics STM32WL5 Series Reference Manual page 44

Contents
38.13.16 CPU2 ROM2 CoreSight peripheral identity register 2
38.13.17 CPU2 ROM2 CoreSight peripheral identity register 3
38.13.18 CPU2 ROM2 CoreSight component identity register 0
38.13.19 CPU2 ROM2 CoreSight peripheral identity register 1
38.13.20 CPU2 ROM2 CoreSight component identity register 2
38.13.21 CPU2 ROM2 CoreSight component identity register 3
38.13.22 CPU2 ROM2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
38.14 CPU2 breakpoint unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
38.14.1 BPU control register (BPU_CTRLR) . . . . . . . . . . . . . . . . . . . . . . . . . 1428
38.14.2 BPU remap register (BPU_REMAPR) . . . . . . . . . . . . . . . . . . . . . . . . 1428
38.14.3 BPU comparator register x (BPU_COMPxR) . . . . . . . . . . . . . . . . . . 1429
38.14.4 BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . . . . 1430
38.14.5 BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . . . . 1430
38.14.6 BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . . . . 1431
38.14.7 BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . . . . 1431
38.14.8 BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . . . . 1432
38.14.9 BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . . . 1432
38.14.10 BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . . . . 1433
38.14.11 BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . . . 1433
38.14.12 BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . . . 1434
38.14.13 CPU2 BPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
38.15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435
39 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
39.1 Device electronic signature registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
39.1.1
39.1.2
39.1.3
39.1.4
40 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
41 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1441
44/1450
(C2ROM2_PIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
(C2ROM2_PIDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
(C2ROM2_CIDR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
(C2ROM2_CIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
(C2ROM2_CIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
(C2ROM2_CIDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
Unique device ID register (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
FLASH size data register (FLASHSIZE) . . . . . . . . . . . . . . . . . . . . . . 1437
Package data register (PKG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
IEEE 64-bit unique device ID register (UID64) . . . . . . . . . . . . . . . . . 1438
RM0453 Rev 5
RM0453