AES hardware accelerator (AES)
Counter (CTR) mode
Legend
The CTR mode uses the AES core to generate a key stream. The keys are then XOR-ed
with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A,
Recommendation for Block Cipher Modes of Operation.
Note:
Unlike with ECB and CBC modes, no key scheduling is required for the CTR decryption,
since in this chaining scheme the AES core is always used in encryption mode for producing
the key stream, or counter blocks.
652/1450
Figure 104. CTR encryption and decryption principle
Counter
key
Encrypt
Plaintext block 1
Ciphertext block 1
Counter
key
Decrypt
input
output
Plaintext block 1
XOR
Ciphertext block 1
Encryption
+1
Counter
value
value + 1
key
Encrypt
Plaintext block 2
Ciphertext block 2
Decryption
+1
Counter
value
value + 1
key
Decrypt
Plaintext block 2
Ciphertext block 2
RM0453 Rev 5
+1
Counter
value + 2
key
Encrypt
Plaintext block 3
Ciphertext block 3
+1
Counter
value + 2
key
Decrypt
Plaintext block 3
Ciphertext block 3
RM0453
MSv42142V1
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?