Table 87. Dmamux Interrupts - STMicroelectronics STM32WL5 Series Reference Manual

DMA request multiplexer (DMAMUX)
Note: The GNBREQ field value can be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
There is no hardware write protection.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.
Trigger overrun and interrupt
If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the DMAMUX_RGSR
register.
Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) when the
usage of the related channel of the DMA controller is completed. Else, upon a new detected
trigger event, there is a trigger overrun due to the absence of an acknowledge (that is, no
served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.
14.5 DMAMUX interrupts
An interrupt can be generated upon:
•
a synchronization event overrun in each DMA request line multiplexer channel
•
a trigger event overrun in each DMA request generator channel
For each case, per-channel in.dividual interrupt enable, status, and clear flag register bits
are available. As a consequence, there are mixed secure and non-secure status and clear
flag bit fields inside a same global status and clear flag interrupt register, depending on the
security of the considered DMAMUX channel.
There are two different secure and non-secure interrupt signals that may be generated,
depending on the security of the DMAMUX channel.
Interrupt signal
dmamux_nonsec_ovr_it
490/1450

Table 87. DMAMUX interrupts

Interrupt event
Synchronization event overrun
on a non-secure channel x of the
DMAMUX request line multiplexer
Trigger event overrun
on a non-secure channel x of the
DMAMUX request generator
RM0453 Rev 5
Event flag Clear bit
SOFx CSOFx
OFx COFx
RM0453
Enable bit
SOIE
OIE