Table 272. Cpu2 Cti Inputs; Figure 388. Embedded Cross Trigger - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Table 271. DWT register map and reset values (continued)
Offset Register name
DWT_CIDR3
0xFFC
Reset value
Refer to
register boundary addresses.
38.7 Cross trigger interface (CTI) and cross trigger matrix (CTM)
CTI and CTM taken together form the CoreSight embedded cross trigger (see
There are two CTI components, one dedicated to the CPU2 and one dedicated to the
CPU1. The CTIs are connected to each other via the CTM. The CTI registers are accessible
to the debugger via the corresponding access port and associated AHB.
The CTIs enable events from various sources to trigger debug activity. For example, a
breakpoint reached in one of the processor cores can stop the other processor.
Each CTI has up to eight trigger inputs and eight trigger outputs. Any input can be
connected to any output, on the same CTI or on another CTI via the CTM.
The trigger input and output signals for each CTI are listed in
No.
0
1
Section 38.8: CPU1 ROM table

Figure 388. Embedded cross trigger

HALTED
®
Cortex -M0+ EDBGRQ
CPU
DBGRESTART
HALTED
®
Cortex -M4 EDBGRQ
CPU
DBGRESTART
Source signal Source component
HALTED
-
and Section 38.13: CPU2 ROM tables
AHB ®
Cortex -M0+ CTI
TRIGIN0
TRIGOUT0
TRIGOUT7
PPB ®
Cortex -M4 CTI
TRIGIN0
TRIGOUT0
TRIGOUT7

Table 272. CPU2 CTI inputs

CPU2 CPU2 halted - Indicates CPU2 is in debug mode.
- Not used
RM0453 Rev 5
Debug support (DBG)
PREAMBLE[27:20]
1 0 1 1 0
for the
Figure
CTM channels [3:0]
MSv60369V2
Table 272 to Table 275.
Comments
1351/1450
0 0 1
388).
1435