Figure 287. Transfer Sequence Flow For Slave Receiver With Nostretch = 1; Figure 288. Transfer Bus Diagrams For I2C Slave Receiver; (Mandatory Events Only) - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface

Figure 287. Transfer sequence flow for slave receiver with NOSTRETCH = 1

Example I2C slave receiver 3 bytes, NOSTRETCH = 0:
RXNE
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd data3
Example I2C slave receiver 3 bytes, NOSTRETCH = 1:
RXNE
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
1068/1450
I2C_ISR.RXNE
=1?
Yes
Read I2C_RXDR.RXDATA

Figure 288. Transfer bus diagrams for I2C slave receiver

ADDR
Address data1
S A
EV1
RXNE
S Address data 1
A
Slave reception
Slave initialization
No

(mandatory events only)

RXNE
RXNE
data2
A A
EV2
RXNE RXNE
data 2 data 3
A A
EV2
EV1
RM0453 Rev 5
No
I2C_ISR.STOPF
=1?
Yes
Set I2C_ICR.STOPCF
RXNE
data3
A
EV3 EV4
P
A
EV3
RM0453
MS19856V2
Legend
Transmission
Reception
SCL stretch
Legend
Transmission
Reception
SCL stretch
MS19857V4