Table 19. Rdp Regression From Level 1 To Level 0 And Memory Erase - STMicroelectronics STM32WL5 Series Reference Manual

Embedded flash memory (FLASH)

Table 19. RDP regression from level 1 to level 0 and memory erase

ESE PCROP
None
Partial
0
Complete
None
Partial
1
partial
Complete
non-secure
1
complete x
flash
None
Partial
1 → 0
Complete
non-secure
Note: Full mass erase or partial mass erase is performed only when level 1 is active and level 0 is
requested. When the protection level is increased (0→1, 1→2, 0→2, or directly decreased
from level 2 to level 0), there is no mass erase.
To validate the protection level change, the option bytes must be reloaded through the
OBL_LAUNCH bit in FLASH_CR, or a POR, or wake-up from Standby or Shutdown mode.
120/1450
PCROP_RDP
x
FLASH, SRAM1, SRAM2, PKA SRAM and backup registers mass erase
1
Flash multiple page erase of all non-PCROP pages
SRAM1, SRAM2, PKA SRAM and backup registers erased (PCROP
flash pages conserved)
0
Flash, SRAM1, SRAM2 and backup registers conserved
PKA SRAM erase.
x Flash multiple page erase of all non-secure pages
SRAM1, SRAM2, PKA SRAM and backup registers erased (secure flash
1
pages conserved)
Flash multiple page erase of all non-PCROP pages and non-secure
pages
SRAM1, SRAM2, PKA SRAM and backup registers erased (PCROP
0
flash pages and secure flash pages conserved)
Flash, SRAM1, SRAM2, and backup registers conserved
PKA SRAM erased
Flash, SRAM1, SRAM2, and backup registers conserved
x
PKA SRAM erased
x
Flash, SRAM1, SRAM2, PKA SRAM and backup registers mass erased
1
Flash multiple page erase of all non-secure non-PCROP pages and
secure pages
SRAM1, SRAM2, PKA SRAM and backup registers erased (non-secure
PCROP flash pages conserved)
0
Flash multiple page erase of all secure pages
SRAM1, SRAM2, PKA SRAM and backup registers erased (non-secure
PCROP flash pages conserved)
Comment
RM0453 Rev 5
RM0453