STMicroelectronics STM32WL5 Series Reference Manual page 920

General-purpose timers (TIM16/TIM17)
The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.
On a given timer event, the timer launches a sequence of DMA requests (burst). Each write
into the TIMx_DMAR register is actually redirected to one of the timer registers.
The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes
a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the
number of transfers (either in half-words or in bytes).
The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA
transfers (when read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
For example, the timer DMA burst feature could be used to update the contents of the CCRx
registers (x = 2, 3, 4) on an update event, with the DMA transferring half words into the
CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
–
–
–
–
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
This example is for the case where every CCRx register is to be updated once. If every
CCRx register is to be updated twice for example, the number of data to transfer should be
6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5
and data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
Note: A null value can be written to the reserved registers.
27.3.18 Using timer output as trigger for other timers (TIM16/TIM17)
The timers with one channel only do not feature a master mode. However, the OC1 output
signal can be used to trigger some other timers (including timers described in other sections
of this document). Check the "TIMx internal trigger connection" table of any TIMx_SMCR
register on the device to identify which timers can be targeted as slave.
The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the
destination timer, to make sure the slave timer detects the trigger.
920/1450
DMA channel peripheral address is the DMAR register address
DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into the CCRx registers.
Number of data to transfer = 3 (See note below).
Circular mode disabled.
RM0453 Rev 5
RM0453