Figure 211. External Trigger Input Block - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
(1)
ETR input or LSE
ETR1..15 inputs from
on-chip sources
1. As per ETR_RMP bit programming.
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. Select the proper ETR source (internal or external) with the ETRSEL[3:0] bits in the
TIMx_AF1 register and the ETR_RMP bit in the TIM2_OR1 register.
2. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
3. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
4. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
5. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal. As a consequence, the maximum frequency
which can be correctly captured by the counter is at most ¼ of TIMxCLK frequency. When
the ETRP signal is faster, the user should apply a division of the external signal by a proper
ETPS prescaler setting.

Figure 211. External trigger input block

ETR
0
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR TIMx_SMCR
ETRSEL[3:0]
TIMx_AF1
ETRP
Divider
Filter
downcounter
f
DTS
ETF[3:0]
TIMx_SMCR
RM0453 Rev 5
General-purpose timer (TIM2)
TI2F or
or
TI1F or
Encoder
mode
TRGI External clock
mode 1
External clock
ETRF
mode 2
CK_INT
Internal clock
mode
(internal clock)
ECE SMS[2:0]
TIMx_SMCR
CK_PSC
MSv47462V1
839/1450
892