Table 205. Wwdg Internal Input/Output Signals; Figure 272. Watchdog Block Diagram - STMicroelectronics STM32WL5 Series Reference Manual

System window watchdog (WWDG)
31.3.1 WWDG block diagram
pclk
31.3.2 WWDG internal signals
Table 205
Signal name
wwdg_out_rst
wwdg_it
31.3.3 Enabling the watchdog
The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.
31.3.4 Controlling the down-counter
This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value,
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 273). The
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
or equal to the window register value, and greater than 0x3F.
window watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
984/1450

Figure 272. Watchdog block diagram

Register interface
W[6:0]
WWDG_CFR
WWDG_SR
readback
WWDG_CR
7-bit downcounter (CNT)
WDGTB
÷ 4096 ÷ 2
gives the list of WWDG internal signals.

Table 205. WWDG internal input/output signals

Signal type
pclk Digital input
Digital output
Digital output
WWDG configuration register (WWDG_CFR)
CMP = 1 when
T[6:0] > W[6:0]
Write to
WWDG_CR
= 0x40 ?
preload
cnt_out
APB bus clock
WWDG reset signal output
WWDG early interrupt output
RM0453 Rev 5
WWDG
WDGA
T6
EWI
EWIF
Description
contains the high limit of the
Figure 273 describes the
RM0453
wwdg_out_rst
wwdg_it
MS47214V2