STMicroelectronics STM32WL5 Series Reference Manual page 689

RM0453
Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
23.7.7 AES key register 2 (AES_KEYR2)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
w w w
15 14 13
w w w
Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
23.7.8 AES key register 3 (AES_KEYR3)
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
w w w w
15 14 13 12
w w w w
Bits 31:0 KEY[127:96]: Cryptographic key, bits [127:96]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
23.7.9 AES initialization vector register 0 (AES_IVR0)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
28 27 26 25
w w w w
12 11 10 9
w w w w
27 26 25
w w w
11 10 9
w w w
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
24 23 22
KEY[95:80]
w w w
8 7 6
KEY[79:64]
w w w
24 23 22 21
KEY[127:112]
w w w w
8 7 6 5
KEY[111:96]
w w w w
24 23 22
IVI[31:16]
rw rw rw
8 7 6
IVI[15:0]
rw rw rw
RM0453 Rev 5
AES hardware accelerator (AES)
21 20 19 18
w w w w
5 4 3 2
w w w w
20 19 18
w w w
4 3 2
w w w
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
w w
1 0
w w
17 16
w w
1 0
w w
17 16
rw rw
1 0
rw rw
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