Figure 334. Lpuart Word Length Programming - STMicroelectronics STM32WL5 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
36.4.4 LPUART FIFOs and thresholds
The LPUART can operate in FIFO mode.
The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). The
FIFO mode is enabled by setting FIFOEN bit (bit 29) in LPUART_CR1 register.
Since the maximum data word length is 9 bits, the TXFIFO is 9-bit wide. However the
RXFIFO default width is 12 bits. This is due to the fact that the receiver does not only store
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Figure 334. LPUART word length programming

9-bit word length (M = 01 ), 1 Stop bit
Start
Bit0 Bit1 Bit2
bit
Clock
8-bit word length (M = 00 ), 1 Stop bit
Start
Bit0 Bit1 Bit2
bit
Clock
7-bit word length (M = 10 ), 1 Stop bit
Start
Bit0 Bit1 Bit2
bit
Clock
Data frame
Bit3 Bit4 Bit5 Bit6 Bit7
Idle frame
Break frame
Possible
Data frame Parity
bit
Bit3 Bit4 Bit5 Bit6 Bit7
**
Idle frame
Break frame
Possible
Data frame Parity
bit
Stop
Bit3 Bit4 Bit5 Bit6
bit
**
Idle frame
Break frame
** LBCL bit controls last data clock pulse
RM0453 Rev 5
Possible
Parity
bit
Next
Stop
Start
Bit8
bit
bit
**
Start
bit
Stop Stop Start
bit bit
bit
Next
Stop
Start
bit
bit
Start
bit
Stop Stop
Start
bit bit bit
Next
Start
bit
Start
bit
Stop Stop
Start
bit bit
bit
RM0453
MS33194V2