STMicroelectronics STM32WL5 Series Reference Manual page 818

Advanced-control timer (TIM1)
25.4.29 TIM1 timer input selection register (TIM1_TISEL)
Address offset: 0x68
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 TI4SEL[3:0]: selects TI4[0] to TI4[15] input
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 TI3SEL[3:0]: selects TI3[0] to TI3[15] input
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
818/1450
28 27 26 25
TI4SEL[3:0]
rw rw rw
12 11 10 9
TI2SEL[3:0]
rw rw rw
0000: TIM1_CH4 input
Others: Reserved
0000: TIM1_CH3 input
Others: Reserved
0000: TIM1_CH2 input
Others: Reserved
0000: TIM1_CH1 input
Others: Reserved
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
RM0453 Rev 5
21 20 19 18
Res. Res. TI3SEL[3:0]
rw rw
5 4 3 2
Res. Res. TI1SEL[3:0]
rw rw
RM0453
17 16
rw rw
1 0
rw rw