STMicroelectronics STM32WL5 Series Reference Manual page 441

RM0453
11.2.12 SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2)
Address offset: 0x104
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PVDIM: PVD interrupt mask to CPU1
0: PVD interrupt forwarded to CPU1
1. PVD interrupt to CPU1 masked
Bit 19 Reserved, must be kept at reset value.
Bit 18 PVM3IM: PVM3 interrupt mask to CPU1
0: PVM3 interrupt forwarded to CPU1
1. PVM3 interrupt to CPU1 masked
Bits 17:0 Reserved, must be kept at reset value.
11.2.13 SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1)
Address offset: 0x108
Reset value: 0x0000 0000
31 30 29
EXTI15 EXTI14 EXTI13 EXTI12
IM IM IM
rw rw rw
15 14 13
Res. Res. DACIM ADCIM
rw
Bits 31:16 EXTIxIM: EXTIx interrupt mask to CPU2 (x = 15 to 0)
0: EXTIx interrupt forwarded to CPU2
1. EXTIx interrupt to CPU2 masked
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 DACIM: DAC interrupt mask to CPU2
0: DAC interrupt forwarded to CPU2
1. DAC interrupt to CPU2 masked
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
EXTI11I EXTI10 EXTI9I
IM M IM M
rw rw rw rw
12 11 10 9
COMPI
AESIM Res.
M
rw rw rw
System configuration controller (SYSCFG)
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22
EXTI8I EXTI7I EXTI6I EXTI5I
M M M
rw rw rw
8 7 6
FLASHI
PKAIM Res. RCCIM
M
rw rw
RM0453 Rev 5
21 20 19 18
PVM3I
Res. PVDIM Res.
M
rw rw
5 4 3 2
Res. Res. Res. Res.
21 20 19 18
EXTI4I EXTI3I EXTI2I
M M M M
rw rw rw rw
5 4 3 2
RTCW RTCSS
Res.
KUPIM RUIM
rw rw rw
17 16
Res. Res.
1 0
Res. Res.
17 16
EXTI1I EXTI0I
M M
rw rw
1 0
RTCST
RTCAL AMPTA
ARMIM MPLSE
CSSIM
rw rw
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