Figure 212. Control Circuit In External Clock Mode 2; Figure 213. Capture/Compare Channel (Example: Channel 1 Input Stage) - STMicroelectronics STM32WL5 Series Reference Manual

General-purpose timer (TIM2)
f CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock =
CK_CNT =CK_PSC
Counter register
26.3.4 Capture/Compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 213. Capture/Compare channel (example: channel 1 input stage)

TI1[0]
TIMx_CH1
TI1[1..15]
f
DTS
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
840/1450

Figure 212. Control circuit in external clock mode 2

Filter
downcounter
TI1F
Edge
detector
ICF[3:0]
TIMx_CCMR1
RM0453 Rev 5
34
TI1F_ED
TI1F_Rising
0
TI1FP1
TI1F_Falling
1
TI2FP1
CC1P/CC1NP
TRC
TIMx_CCER
(from slave mode
controller)
TI2F_Rising
0
(from channel 2)
TI2F_Falling
1
(from channel 2)
35
To the slave mode controller
01
IC1
Divider
10
/1, /2, /4, /8
11
CC1S[1:0] ICPS[1:0]
CC1E
TIMx_CCER
TIMx_CCMR1
RM0453
36
MSv33111V3
IC1PS
MSv40120V1