RM0453
Note:
I2SDIV must be strictly higher than 1.
The following table provides example precision values for different clock configurations.
Note:
Other configurations are possible that allow optimum clock precision.
Table 257. Audio-frequency precision using 48 MHz clock derived from HSE
SYSCLK
(MHz)
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
Serial peripheral interface / integrated interchip sound (SPI/I2S)
Data
I2SDIV
I2SODD
length
16
8
0
32
4
0
16
15
1
32
8
0
16
17
0
32
8
1
16
23
1
32
11
1
16
34
0
32
17
0
16
47
0
32
23
1
16
68
0
32
34
0
16
94
0
32
47
0
16
2
0
32
2
0
16
2
0
32
2
0
16
3
0
32
3
0
16
4
1
32
4
1
16
6
0
32
6
0
16
8
1
32
8
1
16
11
1
32
11
1
RM0453 Rev 5
Target fs
MCLK
(Hz)
No
96000
No
96000
No
48000
No
48000
No
44100
No
44100
No
32000
No
32000
No
22050
No
22050
No
16000
No
16000
No
11025
No
11025
No
8000
No
8000
Yes
48000
Yes
48000
Yes
44100
Yes
44100
Yes
32000
Yes
32000
Yes
22050
Yes
22050
Yes
16000
Yes
16000
Yes
11025
Yes
11025
Yes
8000
Yes
8000
(1)
Real fs (kHz)
Error
93750
2.3438%
93750
2.3438%
48387.0968
0.8065%
46875
2.3438%
44117.647
0.0400%
44117.647
0.0400%
31914.8936
0.2660%
32608.696
1.9022%
22058.8235
0.0400%
22058.8235
0.0400%
15957.4468
0.2660%
15957.447
0.2660%
11029.4118
0.0400%
11029.412
0.0400%
7978.7234
0.2660%
7978.7234
0.2660%
46875
2.3430%
46875
2.3430%
46875
6.2925%
46875
6.2925%
31250
2.3438%
31250
2.3438%
20833.333
5.5178%
20833.333
5.5178%
15625
2.3438%
15625
2.3438%
11029.4118
0.0400%
11029.4118
0.0400%
8152.17391
1.9022%
8152.17391
1.9022%
1293/1450
1311
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