STMicroelectronics STM32WL5 Series Reference Manual page 921

RM0453
For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer,
the OC1 pulse width must be 8 clock cycles.
27.3.19 Debug mode
When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to
peripheral freeze register
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are
disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state
(OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force
them to Hi-Z.
Section 38.12.7: DBGMCU CPU1 APB2
(DBGMCU_APB2FZR).
RM0453 Rev 5
General-purpose timers (TIM16/TIM17)
®
-M4 core halted), the TIMx counter
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