STMicroelectronics STM32WL5 Series Reference Manual page 264

Power control (PWR)
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 LPR: LPRun
Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS[1:0]: Voltage scaling range selection
Bit 8 DBP: Disable backup domain write protection
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 FPDS: Flash memory power-down mode during LPSleep for CPU1
264/1450
When this bit is set, the supply mode is switched from main regulator mode (MR) to low-
power regulator mode (LPR).
Previous voltage range change must be completed before chaining voltage range again.
0b00: Cannot be written (forbidden by hardware)
0b01: Range 1
0b10: Range 2
0b11: Cannot be written (forbidden by hardware)
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and backup registers disabled
1: Access to RTC and backup registers enabled
This bit selects whether the flash memory is in Power-down mode or Idle mode when both
CPUs are in Sleep mode. flash memory is only set in power-down mode when the system is
in LPSleep mode and the PWR_C2CR1.FPDS bit from CPU2 also allows so.
0: Flash memory in Idle mode when system is in LPSleep mode
1: Flash memory in Power-down mode when system is in LPSleep mode
RM0453 Rev 5
RM0453