STMicroelectronics STM32WL5 Series Reference Manual page 318

Reset and clock control (RCC)
Bit 2 MSIRDYIE: MSI ready interrupt enable
Bit 1 LSERDYIE: LSE ready interrupt enable
Bit 0 LSIRDYIE: LSI ready interrupt enable
7.4.6 RCC clock interrupt flag register (RCC_CIFR)
Address offset: 0x01C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSF: LSE CSS (clock security system) flag after masking
Bit 8 CSSF: HSE32 CSS flag
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYF: PLL ready interrupt flag
318/1450
This bit is set and cleared by software to enable/disable interrupt caused by the MSI
oscillator stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
This bit is set and cleared by software to enable/disable interrupt caused by the LSE
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
This bit is set and cleared by software to enable/disable interrupt caused by the LSI
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
LSE
Res. Res.
CSSF
r
This bit is set by hardware when LSECSSIE = 1 and a failure is detected in the LSE
oscillator. It is cleared by software setting the LSECSSC bit.
0: No CSS interrupt caused by LSE clock failure
1: CSS interrupt caused by LSE clock failure
This bit is set by hardware when a failure is detected in the HSE32 oscillator. It is cleared by
software setting the CSSC bit.
0: No clock security interrupt caused by HSE32 clock failure
1: Clock security interrupt caused by HSE32 clock failure
This bit is set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by
software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
24 23 22
Res. Res. Res. Res.
8 7 6
CSSF Res. Res.
RDYF
r
RM0453 Rev 5
21 20 19 18
Res. Res. Res.
5 4 3 2
PLL HSE HSI MSI
RDYF RDYF RDYF
r r r r
RM0453
17 16
Res. Res.
1 0
LSE LSI
RDYF RDYF
r r