Advanced-control timer (TIM1)
25.4.11
TIM1 capture/compare enable register
(TIM1_CCER)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
CC4NP
Res.
CC4P
CC4E
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 CC6P: Capture/Compare 6 output polarity
Bit 20 CC6E: Capture/Compare 6 output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CC5P: Capture/Compare 5 output polarity
Bit 16 CC5E: Capture/Compare 5 output enable
Bit 15 CC4NP: Capture/Compare 4 complementary output polarity
Bit 14 Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output polarity
Bit 12 CC4E: Capture/Compare 4 output enable
Bit 11 CC3NP: Capture/Compare 3 complementary output polarity
Bit 10 CC3NE: Capture/Compare 3 complementary output enable
Bit 9 CC3P: Capture/Compare 3 output polarity
Bit 8 CC3E: Capture/Compare 3 output enable
Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
Bit 6 CC2NE: Capture/Compare 2 complementary output enable
800/1450
28
27
26
25
Res.
Res.
Res.
12
11
10
9
CC3NP CC3NE
CC3P
rw
rw
rw
rw
Refer to CC1P description
Refer to CC1E description
Refer to CC1P description
Refer to CC1E description
Refer to CC1NP description
Refer to CC1P description
Refer to CC1E description
Refer to CC1NP description
Refer to CC1NE description
Refer to CC1P description
Refer to CC1E description
Refer to CC1NP description
Refer to CC1NE description
24
23
22
Res.
Res.
Res.
CC6P
8
7
6
CC3E
CC2NP CC2NE
CC2P
rw
rw
rw
RM0453 Rev 5
21
20
19
18
CC6E
Res.
Res.
rw
rw
5
4
3
2
CC2E
CC1NP CC1NE
rw
rw
rw
rw
RM0453
17
16
CC5P
CC5E
rw
rw
1
0
CC1P
CC1E
rw
rw
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