STMicroelectronics STM32WL5 Series Reference Manual page 492

DMA request multiplexer (DMAMUX)
14.6 DMAMUX registers
Refer to the table containing register boundary addresses for the DMAMUX base address.
DMAMUX registers may be accessed per byte (8-bit), half-word (16-bit), or word (32-bit).
The address must be aligned with the data size.
14.6.1 DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 13)
Reset value: 0x0000 0000
This register must be written by a non-secure or secure write, according to the secure mode
of the considered DMAMUX request line multiplexer channel x, depending on the secure
mode bit of the connected DMA controller channel y. This assumes that the DMAMUX
x channel output is connected to the y channel of the DMA (refer to the DMAMUX mapping
implementation section).
This register must be accessed by a privileged or unprivileged read/write, according to the
privileged mode of the considered DMAMUX request line multiplexer channel x, depending
on the privileged control bit of the connected of the connected DMA controller channel y.
This assumes that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMUX mapping implementation section).
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see ).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field must only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: No event (no synchronization, no detection).
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 SE: Synchronization enable
0: Synchronization disabled
1: Synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
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28 27 26 25
SYNC_ID[4:0]
rw rw rw rw
12 11 10 9
Res. Res. EGE
rw
24 23 22
NBREQ[4:0]
rw rw rw
8 7 6
SOIE
rw rw rw
RM0453 Rev 5
21 20 19 18
SPOL[1:0]
rw rw rw rw
5 4 3 2
DMAREQ_ID[7:0]
rw rw rw rw
RM0453
17 16
SE
rw rw
1 0
rw rw