Shutdown Mode; Table 54. Standby Mode - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Refer to the table below for more details on how to exit Standby mode.
Standby
Mode entry
Mode exit
Wake-up latency Reset phase
6.5.11

Shutdown mode

The lowest power consumption can be reached in Shutdown mode. It is based on the
Deep-Sleep mode, with the voltage regulator disabled. The V
powered off. PLL, HSI16, MSI, LSI and HSE32 oscillators are also switched off.
SRAM1, SRAM2 and registers contents are lost except for registers in the backup domain.
BOR is not available in Shutdown mode. No power voltage monitoring is possible in this
mode, therefore the switch to the backup domain is not supported.
I/O states in Shutdown mode
In Shutdown mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x = A, B, C, H), or with a pull-down (refer to PWR_PDCRx registers (x = A, B, C,
H)), or can be kept in analog state. However this configuration is lost when exiting the
Shutdown mode due to the power-on reset.
The RTC output on PC13 only is functional in Shutdown mode. PC14 and PC15 used for
LSE are also functional. Three wake-up pins (WKUPx, x = 1, 2, 3) and the three TAMP
tampers are available.
Enter Shutdown mode
The Shutdown mode is entered according
Cortex system control register is set (see

Table 54. Standby mode

WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b011 in PWR_CR1 and/or PWR_C2CR1 or higher
– WUFx bits are cleared in power status register 1 (PWR_SR1)
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b011 in PWR_CR1 and/or PWR_C2CR1 or higher
– Radio IRQ is cleared in the sub-GHz radio.
– WPVDF, WRFBUSY and WUFx bits are cleared in power status register 1
(PWR_SR1)
– RTC flag corresponding to the chosen wake-up source (RTC Alarm A, RTC
Alarm B, RTC wake-up, synchronous binary counter or timestamp flags) is
cleared
– TAMP flags ITAMPxF and TAMPxF are cleared.
PVD event, RFIRQ interrupt, RFBUSY wake-up event, WKUPx pin edge, RTC
and TAMP event, external reset in
RM0453 Rev 5
Description
NRST
pin, IWDG reset, BOR reset
CORE
Section 6.5.3, when the SLEEPDEEP bit in the
Table 55 for details).
Power control (PWR)
domain is consequently
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