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RM0453
7.4.44
RCC CPU2 APB1 peripheral clock enable in Sleep mode register 2
(RCC_C2APB1SMENR2)
Address offset: 0x17C
Reset value: 0x0000 0061
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3SMEN: Low-power timer 3 clocks enable during CPU2 CSleep and CStop modes
Bit 5 LPTIM2SMEN: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1SMEN: Low power UART 1 clock enable during CPU2 CSleep and CStop modes
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software.
0: LPTIM3 bus and kernel clocks disabled by the clock gating during CPU2 CSleep and
CStop modes
1: LPTIM3 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
This bit is set and cleared by software.
0: LPTIM2 bus and kernel clocks disabled by the clock gating during CPU2 CSleep and
CStop modes
1: LPTIM2 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
This bit is set and cleared by software.
0: LPUART1 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: LPUART1 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
24
23
22
Res.
Res.
Res.
Res.
8
7
6
LPTIM3
LPTIM2
Res.
Res.
SMEN
SMEN
rw
RM0453 Rev 5
Reset and clock control (RCC)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
17
16
Res.
Res.
1
0
LP
Res.
UART1
SMEN
rw
363/1450
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