STMicroelectronics STM32WL5 Series Reference Manual page 569

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
Analog watchdog 2 status bit is set
Analog watchdog 3 status bit is set
Channel Configuration Ready
End of sampling phase
Overrun
Table 109. ADC interrupts (continued)
Interrupt event
RM0453 Rev 5
Analog-to-digital converter (ADC)
Event flag
Enable control bit
AWD2
AWD3
CCRDY
CCRDYIE
EOSMP
EOSMPIE
OVR
AWD2IE
AWD3IE
OVRIE
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