Figure 341. Reception Using Dma - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in LPUART_CR3 register.
Data are loaded from the LPUART_RDR register to a SRAM area configured using the DMA
peripheral (refer to the corresponding
whenever a data byte is received. To map a DMA channel for LPUART reception, use the
following procedure:
1. Write the LPUART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE (RXFNE in case FIFO mode is enabled) event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from LPUART_RDR to this memory area after each
RXNE (RXFNE in case FIFO mode is enabled) event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
TX line
RXNE flag
DMA request
LPUART_RDR
DMA reads
LPUART_RDR
DMA TCIF flag
(transfer complete)
Software configures
the DMA to receive 3
datablocks and
enables the LPUART
Note: When FIFO management is enabled, the DMA request is triggered by Receive FIFO not
empty (i.e. RXFNE = 1).
Error flagging and interrupt generation in multibuffer communication
If any error occurs during a transaction In multibuffer communication mode, the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in
case FIFO mode is enabled) in single byte reception, there is a separate error flag interrupt
Low-power universal asynchronous receiver transmitter (LPUART)
Direct memory access controller (DMA)

Figure 341. Reception using DMA

Frame 1
Set by hardware
cleared by DMA read
F 1
DMA reads F1
from
LPUART_RDR
RM0453 Rev 5
Frame 2
F2
DMA reads F2 DMA reads F3
from
LPUART_RDR LPUART_RDR
section)
Frame 3
F3
Cleared by
Set by hardware
software
DMA transfer is
complete
from
(TCIF=1 in
DMA_ISR)
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